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Zadavatel obdržel dne 23.2.2024 dotaz k Výzvě k účasti na PTK.
Zadavatel níže poskytuje odpovědi na vznesené dotazy včetně původního znění dotazu vzneseného jedním z účastníků PTK. Dotazy jsou vzneseny v anglickém jazyce. Z tohoto důvodu i zadavatele odpovídá v angličtině. Tuto možnost si zadavatel vyhradil ve Výzvě k účasti na PTK.
Zadavatel současně upozorňuje, že na základě žádosti jednoho z dodavatelů mění termín pro odevzdání Návrhu výpočetního clusteru do 1.3.2024. Zadavatel k tomuto rozhodnutí dospěl zejména z toho důvodu, že dodavatel požadoval minimální posun termínu, a sice o jeden kalendářní den.
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Additionally, can you please address following bolded ( re question 2) :
Question: 2. May you clarify the requirement: "min. 450 GB/s bandwidth to CPU/socket memory". Shall we consider it as max result of STREAM benchmark for the server?
Response of the contracting authority:
This is the expected maximal (theoretical as defined by the memory controller and used DRAM DIMMs) throughput."
Question:
Our detailed question is:
Is it correct that in case of HBM type memory presence in CPU we must consider total I/O throughput/bandwidth for the socket including both memory components HBM and DDR5 (if it works together, e.g. Cache mode for Intel Xeon 4th generation with HBM)?
Answer of the Contracting Authority:
In case the CPU has HBM memory available it's expected that the memory throughput is achieved on the HM part only, but in such a case this must be explicitly stated (that the achievable throughput is on HBM only). It also has to be stated what is the capacity of the HBM memory and thus for which maximum data size the indicated throughput is achievable. If there's additional info about the throughput to the overall memory (so to DDR with HBM serving as a cache) available, we're interested in such an information as well, but will be treated as additional info.
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